SY100S838 chip equivalent, clock generation chip.
* 3.3V and 5V power supply options
* 50ps output-to-output skew
* Synchronous enable/disable
* Master Reset for synchronization
* Internal 75KΩ input .
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The .
The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely al.
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